Fractional dividers can replace Fractional-N Phase Locked Loops (PLLs). Fractional dividers provide power, die size, and transient advantages over conventional PLLs. Conventional fractional dividers typically use a phase interpolator to reduce jitter. A phase interpolator has a relatively stable full-scale phase delay, but suffers from poor linearity and tends to introduce spurs. Attempts to calibrate and linearize phase interpolators have been difficult to implement.
Another conventional solution implements a jitter attenuating PLL. Such approaches have drawbacks such as needing large die sizes to implement. Such approaches tend to use high power.
It would be desirable to implement a fractional divider using a calibrated digital-to-time converter.